June 12, 2001 - Wire Load Independent Logic Synthesis and Timing Closure Please check out our press release for a short description of our Patent Pending Technology. "Copyright (c) 2011 Library Technologies, Inc., All Rights Reserved." ...

CellOpt: Power and Delay Optimization "Finally, we got the flip-flop that you optimized, working on the silicon. Our chip became functional. We gained about 30% on cell area, and that turned out about 4-5% gain on total silicon area utilization. Perhaps we have been too cautious and didn't use th...

Library Technologies, Inc. Announces CCSTEST Library Verification Suite for Current Source Models Saratoga, California, May 19, 2008 - Library Technologies, Inc.(LTI) announced today availability of CCSTEST, library verification tool suite to ascertain the accuracy and completeness of CCS based l...

Technical Papers and Product Literature Please select the articles you are interested from the list by clicking over the select button on the left. Enter your name, name of your company, your phone number and your email address. We need the information items marked with "*". Click over the submit...

July 31, 2001 - Positional Sizing: A Recipe for High Speed and Low Power Cell Libraries Positional sizing of parallel and series transistors has a big impact on cell delay, area and on switching energy. For the same effective delay of a uniformly sized cell, a positionally sized cell can be implemen...